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■論文
山口拓人，佐伯勝敏， “Gap Junctionモデルを用いたハードウェアカオスニューラルネットワーク”，電気学会論文誌C，Vol. 144，No. 7（採録決定）
齊藤健，金子美泉，内木場文男，佐伯勝敏，武藤伸洋，見坐地一人，山下裕玄，後藤田卓志，医療応用に向けたマイクロロボットの開発，生物試料分析，Vol. 45，No. 4，pp.169-173，2022.9.30.
佐々木芳樹，佐伯勝敏，自動補正機構を有するパルス形カオスニューロンモデル，電子情報通信学会論文誌C，Vol.J104-C，No.8，pp.233-239，2021.8.1．
上田拓矢，佐伯勝敏，根口純一，應後剛，織田武浩，反射鏡を用いた指向制御可能な超音波センサシステム，電気学会論文誌A，Vol.139，No.11，pp.527-532，2019.11.1.
佐々木芳樹，佐伯勝敏，低容量化カオスニューロンモデルの出力電圧に対する検討，電気学会論文誌C，Vol.138，No.7，pp.766-773，2018.7.1.
佐伯勝敏，堀口拓，複素インピーダンスを用いた低濃度酸化性ガスセンサ，電気学会論文誌A，Vol.138，No.5，pp.244-249，2018.5.1.
Diana Elizabeth Jimenez Bejarano, Katsutoshi Saeki, Stochastic Resonance in a Pulse-type Cell Body Model，Proc. Nonlinear Theory and Its Applications, The Institute of Electronics, Information and Communication Engineers, Vol. 8, No. 4, pp.279-288, 2017.10．
佐々木芳樹，佐伯勝敏，関根好文，低容量化パルス形カオスニューロンモデル，電気学会論文誌C，Vol. 136, No. 10, pp.1424-1430, 2016.10．
奥山敦司，佐伯勝敏，関根好文，高集積化のための細胞体モデルに対する検討，電気学会論文誌C，Vol.136, No.1, pp.16-21, 2016.1．
大瀧光彦，大和田賢，佐伯勝敏，関根好文，STDP学習則を取り入れたパルス形ハードウェアモデル，電気学会論文誌C，Vol.134, No.10, pp.1485-1491, 2014.10．
Katsutoshi Saeki, Daisuke Nihei, Tatsuya Tatebe, Yoshifumi Sekine,
IC implementation of interstitial cell-based CPG model,
An International Journal, Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, DOI 10. 1007/s10470-014-0349-2, Springer, Published online 17 June 2014.
櫻井翼，中江佑太，佐伯勝敏，関根好文，
メンフクロウに着目した2次元定位用パルス型ハードウェア下丘外側核モデル，
電気学会論文誌C，Vol.134，No.3，pp.369-373，2014.3.
齊藤健，岡崎一人，萩原龍矢，高藤美泉，佐伯勝敏，関根好文，内木場文男，
パルス形ハードウェアニューラルネットワークによるMEMSマイクロロボットの歩行動作制御，
電気学会論文誌C，Vol.133, No.7, pp1094-1100, 2012.7.
佐伯勝敏，中里光志，関根好文，
Λ形負性抵抗素子を用いたカオス発振器を有するΔΣA−D変換器，
電子情報通信学会論文誌C，Vol.J94-C, No.10, pp.334-335, Oct. 2011.
佐伯勝敏，佐々木芳樹，関根好文，
Λ形負性抵抗素子を用いた多値SRAMの低消費電流化，
電気学会論文誌C，Vol. 131, No. 3, pp.528-534, 2011.3.
佐伯勝敏，鬼頭亨東，関根好文，
DSPを用いた心音特徴検出システムに対する検討，
信学論A，Vol.J93-A，No.11，PP.732-738，2010.11.
清水 亮，佐伯勝敏，関根好文，
時系列パターンを保持可能なSTDPを有するパルス形ハードウェアニューラルネットワーク，
電気学会論文誌C，Vol. 129, No. 7, pp. 1198-1204, 2009.7.
Ryo Shimizu, Katsutoshi Saeki, Yoshifumi Sekine,
A Study on the Memory of Temporal Sequences Using a Pulse-type Hardware Neural Network with STDP,
Special Issue of Nihon University CST 2008 Annual Conference -Report of RISTNU-, No. 3, pp. 39-42, Mar. 2009.
Ryo Shimizu, Katsutoshi Saeki, Yoshifumi Sekine,
Synaptic Circuit Using STDP with a Mexican-Hat Time Window,
Special Issue of Nihon University CST 2007 Annual Conference -Report of
RISTNU-, No. 2, pp. 133-136, Mar. 2008.
秦恵子，関根好文，中洞芳史，佐伯勝敏，四足歩行運動パターンを生成・移行可能なパルス形ハードウェアCPGモデル，電気論C，Vol.127, No.1, pp. 52-58, 2007. 1.
Katsuyuki Ono, Yoshifumi Sekine, Katsutoshi Saeki,
Non-synchronous Pulse-Type Neural Network Using Strip-Line Structures,
Special Issue of Nihon University CST 2006 Annual Conference -Report of RISTNU-, pp. 137-140, Mar. 2007.
Naoya Sasano, Katsutoshi Saeki, Yoshifumi Sekine,
Short-term memory circuit using hardware ring neural networks,
Artificial Life and Robotics, vol.9, no. 2, pp.81-85, June 2005.
Katsutoshi Saeki, Heisuke Nakashima, Yoshifumi Sekine,
CMOS Implementation of a Multiple-Valued Memory Cell Using Λ-Shaped Negative-Resistance Devices,
The Institute of Electronics, Information and Communication Engineers Transaction on Fundamentals of
Electronics, Communications and Computer Science, Vol. E87-A, No. 4, pp. 801-806, Apr. 2004.
Zongyang Xue, Haruki Nagami, Kazutaka Someya, Katsutoshi Saeki and Yoshifumi Sekine,
A Study of Nonlinear Characteristics in a Hardware Active Dendrite Model,
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences，vol. E86-A, no. 9, pp. 2287-2293, September 2003.
Katsutoshi Saeki and Yoshifumi Sekine,
CMOS Implementation of Neuron Models for an Artificial Auditory Neural Network,
IEICE Trans. Fundamentals, vol. E86-A, no. 2, pp.424-427, Feb. 2003.
佐伯勝敏，関根好文，合原一幸，“エンハンスメント型MOSFETを用いたパルス形バーストニューロンモデル，”電子情報通信学会論文誌C，vol. J85-C，no. 3，pp. 174-180，2002. 3.
Jun Matsuoka, Yoshifumi Sekine, Katsutoshi Saeki and Kazuyuki Aihara,
“Analog Hardware Implementation of a Mathematical Model of an Asynchronous Chaotic Neuron,”
IEICE Trans. Fundamentals, vol. E85-A, no. 2, pp. 389-394, Feb. 2002.
関根好文，隅山正巳，佐伯勝敏，合原一幸，“エンハンスメント型MOSFETによるΛ形ニューロンモデル，” 電子情報通信学会論文誌C，vol. J84-C，no. 10，pp. 988-994，2001. 10.
佐伯勝敏，関根好文，合原一幸，“パルス形ハードウェアバーストニューロンモデル，” 電子情報通信学会論文誌C，vol. J83-C，no. 3，pp. 213-219，2000. 3.
■解説
佐伯勝敏，戸泉孝太，上田拓矢，2020年，感動をエンジニアリングする〜NHK放送技術研究所〜，電気学会誌，Vol.138，No.6，pp.327-330，2018.6.1.
大谷昭仁, 仲嶋一, 佐伯勝敏, 飴谷充隆, 黒田千愛，計測技術における研究開発の動向と最前線，電気学会論文誌A，Vol.138，No.1，pp.16-21，2018.1.1
関根好文，佐伯勝敏，カオス発生可能なパルス形ハードウェアニューロンモデルの実装とその応用，日本神経回路学会誌，Vol. 15, No. 1, pp. 27-38, 2008.3.
■著書
佐伯勝敏，“2足/4足歩行ロボット制御の実験に！ディスクリート中枢パターン発生器”，トランジスタ技術，10月号，CQ出版社，pp.94-101， 2020.9.10.
Katsutoshi Saeki, Taku Horiguchi, Oxidizing Gas Sensor with Low Concentration using Complex Impedance, Wiley，DOI: 10.1002/ecj.12095, pp.1-7, 4 July 2018.
Ken Saito, Akihiro Matsuda, Katsutoshi Saeki, Fumio Uchikoba and Yoshifumi Sekine,
Synchronization of Coupled Pulse-Type Hardware Neuron Models for CPG Model,
The Relevance of the Time Domain to Neural Network Models Springer Series in Cognitive and Neural Systems, 2012, Volume 3, pp.117-133, Oct. 2011.
Katsutoshi Saeki, Ryo Shimizu, Yoshifumi Sekine,
Pulse-Type Hardware Neural Network with Two Time Windows in STDP,
M. Koppen et al. (Eds.): ICONIP 2008, Part II, LNCS 5507, pp. 877?884, Springer-Verlag Berlin Heidelberg, 2009.
Yugo Hayashi, Katsutoshi Saeki, Yoshifumi Sekine,
A Synaptic Circuit of a Pulse-Type Hardware Neuron Model with STDP,
Technical paper in International Congress Series 1301 Elsevier, pp. 132-135, Jul. 2007.
Keiko Hata, Katsutoshi Saeki, Yoshifumi Sekine,
A Pulse-Type Hardware CPG Model for Quadruped Locomotion Pattern,
Technical paper in International Congress Series 1291 Elsevier, pp. 157-160, Jul. 2006.
Katsutoshi Saeki, Yoshifumi Sekine and Kazuyuki Aihara,
“Chaos in a Pulse-type Hardware Neuron Model,”
' Chaos in Circuits and Systems ' Edited by G. Chen and T. Ueta, pp. 277-295, World Scientific Publishing Co. Singapore, 2002. 4.
■国際会議
Takuto Yamaguchi，Katsutoshi Saeki, Yoshiki Sasaki, A Pulse-Type Hardware Chaotic Neural Network with Gap Junctions for IC Implementation, Proc. International Conference on Analog VLSI Circuits, B2.5, pp.138-142, Online, 19 October 2021.
Yoshiki Sasaki, Katsutoshi Saeki, A Pulse-Type Hardware Chaotic Neuron Device with a Negative Resistance Control Circuit Implemented Using a 0.18μm CMOS Process, Proc. International Conference on Analog VLSI Circuits, B2.6, pp.143-147, Online, 19 October 2021.
Yuma Karakama, Tsuyoshi Misumi, Katsutoshi Saeki, Synaptic Hardware Model Depending on High Frequency Stimulation and Oscillation Frequency, Proc. International Technical Conference on Circuits/Systems, Computers and Communications, 1B-1, pp.21-24, Online, 3 July 2020.
Mika Kurosawa, Takuro Sasaki, Masaya Ohara, Taisuke Tanaka, Yuichiro Hayakawa, Minami Kaneko, Fumio Uchikoba, Katsutoshi Saeki, Ken Saito, Gait Pattern Generation of Hexapod-Type Microrobot Using Interstitial Cell Model Based Hardware Neural Networks IC, Proc. International Conference on Electronics Packaging, Niigata, 19 April 2019.
Takahiro Toizumi and Katsutoshi Saeki, Central Pattern Generator based on Interstitial Cell Models made from Bursting Neuron Models, Proc. International Conference on Neural Information Processing, LNCS11302, Part II, pp.321-329, Springer, Siem Reap, Cambodia, 14 December 2018.
Takuya Ueda, Jyunichi Neguchi, Takeshi Ohgo, Takehiro Orita, Katsutoshi Saeki, A Study on Directional Control of Ultrasonic Sensor Using a Couple Reflector, Proc. International Technical Conference on Circuits/Systems, Computers and Communications, CS-04, PID190，pp.74-77, Bangkok, Thailand, 5 July 2018.
Takuya Ueda, Jyunichi Neguchi, Takeshi Ohgo, Takehiro Orita, Katsutoshi Saeki,
Directional Control of Ultrasonic Sensor Using Parabolic Radiation-type Reflector, Proc. International Congress on Ultrasonics, Honolulu, U.S.A., 19 December 2017.
Taku Horiguchi, Katsutoshi Saeki,
Gas Selectivity of Low-Concentration Oxidizing-Gas Sensor using Complex Impedance Method, Proc. IEEE Control and System Graduate Research Colloquium, B1-40, pp.160-164, Shah Alam, Malaysia, 5 August 2017.
Katsutoshi Saeki, Daisuke Nihei,
VLSI Implementation of a Hardware CPG Model for Biped Robots,
Proc. International Conference on Analog VLSI Circuits, pp.93-98, Boston, U.S.A., 25. Aug. 2016.
Takahiro Toizumi, Yoshiki Sasaki, Katsutoshi Saeki,
Implementation of Low Power Consumption of Neuromorphic Devices,
Proc. International Technical Conference on Circuits/Systems, Computers and Communications, T2-2-5, pp.499-502, Naha, Okinawa, 12 July 2016.
Taku Horiguchi, Yoshiki Sasaki, Katsutoshi Saeki,
Moisture-Insensitive Low-Concentration Oxidizing-Gas Sensor,
Proc. International Technical Conference on Circuits/Systems, Computers and Communications, M3-2-4, pp.303-306, Naha, Okinawa, 11 July 2016.
Daichi Yamashita, Katsutoshi Saeki, Yoshifumi Sekine,
IC Implementation of Spike-timing-dependent-Synaptic Plasticity Model Using Low Capacitance Value,
2014 IEEE Asia Pacific Conference Circuits and Systems, A4P-D-11, pp.221-224, Okinawa, Japan, 18 Nov. 2014.
Katsutoshi Sugiyama, Katsutoshi Saeki, Minoru Saito, Yoshifumi Sekine,
A Study on Gas Sensor Using SAW Device,
2014 IEEE Asia Pacific Conference Circuits and Systems,B4L-C-01, pp.459-462, Okinawa, Japan, 19 Nov. 2014.
Katsutoshi Saeki, Daisuke Nihei, Tatsuya Tatebe, Yoshifumi Sekine,
An Interstitial Cell-based CPG Device Model Implemented using a 0.18μm CMOS Process,
Proc. International Conference on Analog VLSI Circuits, pp.80-85, Montreal, Canada, 17. Oct. 2013.
Atsushi Okuyama, Katsutoshi Saeki, Yoshifumi Sekine,
A Study on Cell Body Model Considering Total Ionizing Dose Effects,
Proc. International Technical Conference on Circuits/Systems, Computers and Communications, TB3-6, pp.232-235, Yeosu, Korea, 2 July 2013.
Ken Ohwada, Katsutoshi Saeki, Yoshifumi Sekine,
A Study on Firing Waveform Propagation of Neuron Based on Pulse-type Hardware Model,
Proc. International Technical Conference on Circuits/Systems, Computers and Communications, TF2-3, pp.725-728, Yeosu, Korea, 2 July 2013.
Shinnosuke Asai, Katsutoshi Saeki, Minoru Saito, Yoshifumi Sekine,
A Study on Odor Sensors Using Copper Phthalocyanine,
Proc. International Technical Conference on Circuits/Systems, Computers and Communications, C-W2-04, CD-ROM, Sapporo, Japan, 18 July 2012.
Ikuma Wada, Katsutoshi Saeki, Yoshifumi Sekine,
Dithering Effects of a Multi-Bit Delta-Sigma Analog-to-Digital Converter Using Chaotic Oscillator,
Proc. International Technical Conference on Circuits/Systems, Computers and Communications, B-M2-06, CD-ROM, Sapporo, Japan, 16 July 2012.
Yuichi Mashimo, Yoshiki Sasaki, Katsutoshi Saeki, Yoshihumi Sekine,
Construction of Synaptic Model Using Multiple-Valued SRAM for STDP and Its Application,
Proc. International Technical Conference on Circuits/Systems, Computers and Communications, C-M2-03, CD-ROM, Sapporo, Japan, 16 July 2012.
Katsutoshi Saeki, Tatsuya Tatebe, Yoshifumi Sekine,
A Study on CPG Model Transition Swing and Stance Pattern with Interstitial Cells,
Proc. International Joint Conference on Neural Networks, 264, pp177-184, Brisbane, Australia, 11.June. 2012.
Katsutoshi Saeki, Toshiharu Morita, Yoshifumi Sekine,
Associative Memory Using Pulse-type Neural Network with STDP Synapses,
Proc. International Conference on Intelligent Systems Design and Applications, GS16, pp.947-951, Cordoba, Spain, Nov. 2011.
Katsutoshi Saeki, Shingo Watanabe, Toshiharu Morita, Yoshifumi Sekine,
Pulse-Type Neuro Devices with Two Time Windows in STDP and Its Application to the Memory of Temporal Sequences Patterns,
Proc. International Conference on Biomedical Electronics and Devices, pp.426-431, Rome, Italy, Jan. 2011.
Katsutoshi Saeki, Ryo Shimizu, Yoshifumi Sekine, A PULSE-TYPE HARDWARE NEURON MODEL WITH STDP FOR BRAIN-LIKE INFORMATION PROCESSING SYSTEM,
Computational Intelligence 2009, Honolulu, Hawaii, USA, August, 2009.
Ken Saito, Katsutoshi Saeki, Yoshifumi Sekine,
Synchronization of Coupled Pulse-Type Hardware Neuron Models for CPG Model,
Proceedings of International Joint Conference on Neural Networks, pp. 2748-2755, Atlanta, Georgia, USA, June, 2009.
Katsutoshi Saeki, Ryo Shimizu, Yoshifumi Sekine,
Pulse-Type Hardware Neural Network with Two Time Windows in STDP,
Proc. 2008 International Conference on Neural Information Processing, Auckland, New Zealand, Nov. 23. 2008.
Katsutoshi Saeki, Yoshifumi Sekine,
CMOS Implementation of Intelligent Electronics for Brain-Type Information Processing Systems,
Proc. 2008 International Symposium on Integration of MEMS and Intelligent Electronics, A-02, pp.17-20, Tokyo, Japan, Aug. 23.2008.
Katsutoshi Saeki, Yugo Hayashi, Yoshifumi Sekine,
PULSE-TYPE NEURO DEVICES WITH SPIKE TIMING DEPENDENT SYNAPTIC PLASTICITY,
Proc. International Conference on Biomedical Electronics and Devices, pp.264-268, Funchal, Madeira, Portugal, Jan. 2008.
Katsutoshi Saeki, Yugo Hayashi, Yoshifumi Sekine,
Noise Tolerance of a Pulse-type Hardware Neural Network with STDP
Synapses ?Thermal Noise and Extraction of Phase Difference Information
?, Proc. 2007 IEEJ International Analog VLSI Workshop, pp.88-93,
Shannon, Ireland, Nov. 2007.
Katsutoshi Saeki, Yugo Hayashi, Yoshifumi Sekine,
Robustness of a Pulse-type Hardware Neural Network with STDP Synapses,
Proc. 2006 IEEJ International Analog VLSI Workshop, CD-ROM, Hangzhou,
China, Nov. 2006.
Yugo Hayashi, Katsutoshi Saeki, Yoshifumi Sekine, A
Synaptic Circuit of a Pulse-Type Hardware Neuron Model with STDP, The
Third International Conference on Brain-inspired Information Technology
(Brain IT 2006), p. 60, Kitakyusyu, Sep. 2006.
Katsutoshi Saeki, Yugo Hayashi, Yoshifumi Sekine,
Extraction of Phase Information Buried in Fluctuation of a Pulse-type
Hardware Neuron Model Using STDP, 2006 International Joint Conference
on Neural Networks (IJCNN2006), pp. 2814-2819, Vancouver, Canada, Jul.
2006.
Takashi Inoue, Katsutoshi Saeki, Yoshifumi Sekine, A
Study on an Pattern Recognition of an Olfactory Bulb Model using
Pulse-Type Neuron Models, The International Technical Conference on
Circuits/Systems, Computers and Communications (ITC-CSCC2006), vol.
III, pp. III-409-III-412, Chiang Mai, Thailand, Jul. 2006.
Katsuyuki Ono, Yoshifumi Sekine, Katsutoshi Saeki, A
Study on a Pulse-Type Neural Network Using Strip-Line Structures, The
International Technical Conference on Circuits/Systems, Computers and
Communications (ITC-CSCC2006), vol. I, pp. I-261-I-264, Chiang Mai,
Thailand, Jul. 2006.
Chao-kai CHANG, Katsutoshi SAEKI, Yoshifumi SEKINE, A
Colpitts-Type Crystal Oscillator with a Common-base Circuit for
Gigahertz Frequency Band, Proc. 2005 IEEJ International Analog VLSI
Workshop, CD-ROM, Bordeaux, France, Oct. 2005.
Hatsavanh HAIMANY, Katsuyuki ONO, Katsutoshi SAEKI,
Yoshifumi SEKINE, New Connecting Factors, Incorporated in a Pulse-Type
Hardware Neuron Model, Changes Plasticity in Analog VLSI Design, Proc.
2005 IEEJ International Analog VLSI Workshop, CD-ROM, Bordeaux, France,
Oct. 2005.
Keiko Hata, Katsutoshi Saeki, Yoshifumi Sekine, A
Pulse-Type Hardware CPG Model for Quadruped Locomotion Pattern, The
Second International Conference on Brain-inspired Information
Technology, p. 55, Kitakyusyu, Oct. 2005.
Katsutoshi Saeki, Atsufumi Takeda, Yoshifumi Sekine,
Temporal Pattern Recognition Circuit Using Hardware Ring Neural
Networks, 2004 IEEJ International Analog VLSI Workshop, pp. 245-249,
Oct. 2004.
Yoshifumi Nakabora, Katsutoshi Saeki, Yoshifumi
Sekine, Synchronization of Coupled Oscillators Using Pulse-Type
Hardware Neuron Models with Mutual Coupling, The 2004 International
Conference on Circuits/Systems, Computers and Communications, pp.
8D2L-3-1-8D2L-3-4, Jul. 2004.
Masashi Muragi, Katsutoshi Saeki, Yoshifumi Sekine,
Propagation of Pulses in a Closed-Loop Neural Network Using Pulse-Type
Hardware Neuron Models, The 2004 International Conference on
Circuits/Systems, Computers and Communications, pp. 8D2L-5-1-8D2L-5-4,
Jul. 2004.
Naoya Sasano, Katsutoshi Saeki and Yoshifumi Sekine,
Short-term memory circuit using hardware ring neural networks, Proc.
2004 Artif. Life and Robotics, GS21-1，pp.123-127，Oita Japan, 2004. 1.
K. Saeki，R. Iidaka, Y. Sekine and K.
Aihara,HARDWARE NEURON MODELS WITH CMOS FOR AUDITORY NEURAL
NETWORKS,Proc. 2002 International Conference on Neural Information
Processing (ICONIP02), pp.1325-1329, Singapore, 2002. 11.
Z. Xue, H. Nagami, K. Someya, K. Saeki and Y. Sekine,
Effects of Backpropagation Characteristics in a Hardware Active
Dendrite Model, Proc. International Sumposium on Nonlinear Theory and
its Applications (NOLTA'02), pp. 925-928, Xi'an, Chaina, 2002. 10.
Z. Xue, K. Saeki and Y. Sekine, A PULSE-TYPE HARDWARE
NEURON MODEL, Proc. of the 4th Joint Seminar of NU-XUT, pp. 68-76,
Nihon Univ., 2002. 9.
K. Saito, K. Saeki，and Y. Sekine,The Phase Plane of a
Pulse-type Hardware Neuron Model,Proc. 2002 IEEJ Internatinal Analog
VLSI Workshop, pp. 116-121, Singapore, 2002. 9.
T. Fujita, J. Matsuoka，K. Saeki，Y. Sekine, CMOS
Synaptic Model Considering Spatio-Temporal Summation of Inputs, Proc.
The 2002 Internatinal Technical Conference on Circuits/Systems,
Computers and Communications (ITC-CSCC02), pp. 1188-1191, Phuket,
Thailand, 2002.7.
J. Matsuoka, Y. Sekine, K. Saeki and K. Aihara,
“Pulse-type Hardware Chaotic Neuron Model Constituting from CMOS
Process,” Proc. 2002 International Symposium on Artificial Life and
Robotics (AROB02), vol. 1, S1-3, pp. 62-65, Oita, Japan, 2002. 1.
Z. Xue, M. Itagaki, K. Someya, K. Saeki and Y.
Sekine, “A Hardware Active Dendrite Model,” Proc. 2001 International
Conference on Neural Information Processing (ICONIP01), vol. 3, pp.
1219-1224, Shanghai, China, 2001. 11.
J. Matsuoka, H. Nakashima, K. Saeki, Y. Sekine and K.
Aihara, “The Response Characteristics of a Pulse-type Hardware Chaotic
Neuron Model using CMOS,” Proc. The 2001 International Technical
Conference on Circuits/Systems, Computers and Communications
(ITC-CSCC01), E4-5, pp. 612-615, Tokushima, Japan, 2001.7.
K. Saeki, N. Kashiwagi, Y. Sekine and K. Aihara,
“Pulse-Type Hardware Bursting Neuron Model for IC,” Proc. 2001 IEEJ
International Analog VLSI Workshop, pp. 7-12, Bangkok, Thailand, 2001.
5.
Y. Sekine, J. Matsuoka, K. Saeki and K. Aihara,
“Analog Circuits of Chaotic Neuron Model based on Mathematical
Equations,” Proc. 2001 IEEJ International Analog VLSI Workshop, pp.
25-30, Bangkok, Thailand, 2001. 5.
K. Saeki, Y. Sekine, K. Someya, and K. Aihara,
“Pulse-type Hardware Chaotic Neuron Model using CMOS,” Proc. 2000
International Symposium on Nonlinear Theory and Its Applications
(NOLTA00), vol. 2, Dresden, Germany, pp. 23-26, 2000. 9.
Y. Sekine, K. Someya, K. Saeki, and K. Aihara, “A
Study on Neuronal Coding Using Pulse-Type Hardware Chaotic Neuron
Model,” Proc. The 3rd International Workshop on Neuronal Coding'99
(NCWS99), Osaka, Japan, pp. 121-124, 1999. 10.
K. Saeki, Y. Sekine, and K. Aihara, “A Study on a
Pulse-type Hardware Neuron Model using CMOS,” Proc. 1999 International
Symposium on Nonlinear Theory and Its Applications (NOLTA99), vol. 2,
Hawaii, U. S. A., pp. 855-858, 1999. 12.
K. Someya, A. Fujita, K. Saeki, Y. Sekine, and K.
Aihara, “Effects of an Active Feature on Neurodynamics and Chaotic
Phenomena by Active Axon,” Proc. 1998 International Conference on
Neural Information Processing (ICONIP98), vol. 3, Kita-Kyushu, Japan,
pp. 1273-1276, 1998. 10.
K. Someya, A. Fujita, K. Saeki, and Y. Sekine,
“Neurodynamics and Chaotic Phenomena by Active Axon in Artificial
Neural Networks,” Proc. 1998 IEEE International Joint Conference on
Neural Networks (IJCNN98), Anchorage, Alaska, U. S. A., pp. 1460-1465,
1998. 5.
K. Someya, A. Fujita, K. Saeki, and Y. Sekine,
“Dynamics of Pulse Type Hardware Chaotic Neuron Model with Active
Axon,” Proc. 1997 International Symposium on Nonlinear Theory and Its
Applications (NOLTA97), vol. 1, Hawaii, U. S. A., pp. 641-644, invited
in 1997. 12.
K. Saeki, and Y. Sekine, “Pulse-type Hardware Neuron
Model with Bursting Firing Phenomena,” Proc. of the International
Technical Conference on Circuit/Systems, Computers and Communications
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